1. Field of the Invention
The present invention relates generally to a packet switching equipment and a switching control method. More particularly, the invention relates to a switching control system in a packet switching equipment for switching a packet between a particular input port and a particular output port by employing packet communication technology, such as ATM (Asynchronous Transfer Mode), IP (Internet Protocol) and so forth.
2. Description of the Related Art
Conventionally, a packet switching equipment of this kind is constructed with input buffer portions 1-1 to 1-n [input buffer portions 1-2 to 1-(n−1) are eliminated from illustration] which will be occasionally identified by reference numeral 1 as generally referred to, an arbiter portion 2 and a switch core portion 5 as shown in FIG. 11.
The switch core portion 5 performs switching of the packet between input ports 100-1 to 100-n[input ports 100-2 to 100-(n−1) are eliminated from illustration] which will be occasionally identified by reference numeral 102 as generally referred to, and output ports 101-1 to 101-n [output ports 101-2 to 101-(n−1) are eliminated from illustration] which will be occasionally identified by reference numeral 101 as generally referred to.
Each of input buffer portions 1-1 to 1-n includes logic queue 11-1 to 11-n [logic queues 11-2 to 11-(n−1) are eliminated from illustration] which will be occasionally identified by reference numeral 11 as generally referred to, a packet input portion 12 and a packet output portion 13 and temporarily store the packets arriving to the input ports 100-1 to 100-n. The arbiter portion 2 performs arbitration of output demand from the input buffer portions 1-1 to 1-n for outputting an output permission depending upon result of arbitration and applies opening and closing command to points of intersections in the switch core portion 5.
As the switch core portion 5, as shown in FIG. 12, it has been considered a construction for opening and closing (ON/OFF) of the points of intersections 50 of transmission paths extending in grating form. In this construction, when a plurality of input ports 100 transmit packets to a particular output port 101 simultaneously, packet collision is caused for breakage of data transferred by the packets. Therefore, at the same timing, the input port 100 to transmit the packet to the particular output port has to be limited to one.
Next, discussion will be given for operation of the conventional packet switching equipment. The packets arriving to the input ports 100-1 to 100-n are stored in the logic queues 11-1 to 11-n in the respective input buffer portions. The input buffer portions 1-1 to 1-n check destination output ports 101-1 to 101-n from header information of the leading packets of the logic queues 11-1 to 11-n and notify an output demand for outputting to a destination output port, to the arbiter portion 2 by an output demand signal.
The arbiter portion 2 aggregates output demand signals from all input buffer portions 1-1 to 1-n. When output demands from a plurality of input buffer portions 1-1 to 1-n are present for the same output ports 101-1 to 101-n (upon occurrence of conflict), arbitration is performed for providing an output permission only for selected one of the input buffer portions 1-1 to 1-n. 
The arbiter portion 2 performs arbitration for avoiding packet collision at all output ports 101-1 to 101-n. Thereafter, acceptance and rejection of demand is notified to the input buffer portions 1-1 to 1-n by using the output permission signal. The input buffer portion n which is accepted the demand transmits the leading packet to the switch core portion 5. The switch core portion 5 opens and closes the points of intersections 50 for switching the predetermined output ports 101-1 to 101n on the basis of the result of arbitration obtained from the arbiter portion 2.
As shown in FIG. 13, in the above-mentioned conventional packet switching equipment, when the arbiter portion 2 made decision to permit outputting to the output port #2 for the input buffer #0 which contains the leading packet designated to the output port #2, the output permission for outputting to the output port #2 is given for the input buffer #0 from the arbiter portion 2. At the same time, the switch core portion 5 is commanded to close the point of intersection between the input port #0 and the output port #2 and is controlled so that packet can be switched between the objected ports.
As set forth above, the conventional construction requires control of the switch core portion 5 corresponding to the content of decision in the arbiter portion 2 and thus requires synchronous operations of the input buffer portions 1-1 to 1-n, arbiter portion 2 and the switch core portion 5 without disturbance to make control structure of the switch core portion 5 complicate.